Wireless communication technology and its applications have made tremendous influences in various aspects of modern society. In the past decades, numerous technical breakthroughs have been realized in wireless communication techniques. These advances are represented by the wide adoption of highly efficient access techniques, such as code division multiple access (CDMA), the integration of digital coding/decoding and digital signal processing techniques into a wireless communication device, and the rapid progress in semiconductor manufacturing techniques that enables integrating a large amount of microelectronic circuits on a semiconductor integrated circuit (IC) die. These progresses have led to wireless communication products of today's, such as a mobile phone, to provide a wide spectrum of high-quality functions and services to their users. In the mean time, progress in semiconductor IC manufacturing technology has significantly reduced the costs associated with making wireless communication products. As a result, market penetration of wireless communication products has been spreading from developed countries to the developing world at a rapid pace.
Due to its low-power, low-cost features, Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing technology is typically adopted today in manufacturing wireless communication ICs. This includes fabricating an RF front module using CMOS technology. When receiving wireless information, an RF front module processes RF signals received from an antenna and converts the RF signals to baseband signals suitable for further processing. When transmitting wireless information, an RF front module modulates baseband signals to an RF band and transmits the RF signals through an antenna. An RF front module generally includes RF circuits of various kinds, such as low noise amplifier (LNA), frequency synthesizer, mixer, filter, power amplifier, and/or other analog circuits of pre-defined functions. Among other things, an RF circuitry typically includes RF passive components such as inductors and capacitors of large parametric value and large physical footprint. An RF front module plays a critical role on the overall performance of a wireless communication device.
In an existing approach of fabricating RF front module, a typical CMOS technology processing flow is employed to form active and passive components of various kinds in an RF front module. For example, components such as MOS transistors, resistors, MOS capacitors are formed in a monolithic silicon substrate through an existing Front-End-of-Line (FEOL) process flow. Interconnect metal layers are formed over the silicon substrate through an existing Back-End-of-Line (BEOL) process flow. Dielectric layers, such as silicon dioxide (SiO2) layers are formed between adjacent interconnect metal layers, electrically insulating metal traces formed in different metal layers. Also, on-chip inductors such as planar spiral inductors, typically with a large form factor, are formed in the topmost available metal layers through the BEOL process flow. These on-chip inductors are formed and electrically coupled to other components on the silicon substrate through traces formed in the various interconnect metal layers.
Although widely used, this existing approach of fabricating RF front module poses a few drawbacks. First, materials and processing conditions in an existing CMOS process flow are not tailored for the ideal performance of on-chip inductors. As an example, an on-chip inductor formed over the doped silicon substrate as described above exhibits a poor quality factor (Q factor) when compared with a similar inductor formed over a dielectric material, such as a glass substrate. This is described in “A Power-Optimized Widely-Tunable 5 GHz Monolithic VCO in a Digital SOI CMOS Technology on High Resistivity Substrates” by J. Kim, IEEE ISLPED 2003. Second, in current practice, the silicon areas under the on-chip inductors are typically left blank in an effort to avoid the undesirable eddy currents induced in the silicon substrate due to the varying magnetic flux from the on-chip inductors. This drawback poses a significant limitation on further reducing the form factor of an RFIC. Although temporary solutions have been proposed, none of the existing solutions are without pitfalls. For example, in one approach, on-chip inductors are displaced to a separate region on an RFIC, and are coupled to other components through horizontal electrical feed-throughs. These horizontal feed-throughs, however, generally increase the footprint size of an RFIC. Among other drawbacks of the existing approach, horizontal feed-throughs create crossing signal lines that may affect circuit performance, lengthy horizontal signal line routings may increase signal latency, and long metal traces may lead to undesirable inductance.